1. Field of the Invention
The present invention generally relates to computer modeling of electronic systems, and more specifically, to a computerized electronic system modeling and simulation technique that uses both actual and approximated/estimated properties of the system. Although the present invention will be described in connection with computer aided modeling of a portion of a parallel processor, other utilities are also contemplated for the present invention, including modeling of other types of electronic systems, and features and components thereof, and in other types of computer aided design applications.
2. Brief Description of Related Prior Art
Typically, during the process of formulating and validating a proposed electronic system design, it has been desirable to use computer aided design (CAD) techniques to model and simulate the operation of the proposed design, prior to physically fabricating the proposed system. By employing such modeling and simulation techniques, it is often possible to determine whether potential problems (i.e., design faults) are present in the proposed design, and if necessary, to modify the proposed design to reduce or eliminate such potential problems, without ever physically constructing and testing the system being designed. Thus, by employing such modeling and simulation techniques, the cost and time required to validate a proposed design may be significantly reduced.
However, it has been found that in order to meaningfully model and simulate the operation of certain systems, special considerations must be taken into account. For example, a high speed, high performance parallel processor includes a significant amount of high speed, sequential logic and other clocked circuitry whose proper operation often is critical to proper performance of the parallel processor. Therefore, at most, only minor timing faults in such circuitry can be permitted, if the system is to function acceptably. Thus, in order to meaningfully simulate the operation of a proposed parallel processor design, the timed operation of the parallel processor's clocked circuitry must be simulated with a high degree of accuracy. This need is particularly acute with respect to timing operations involving parallel processor circuit modules that are interconnected by intermodule network connections, as such network connections typically exhibit a relatively large amount of impedance and capacitance that may introduce significant propagation delays into signals traversing the network. This necessitates that the CAD system be able to determine very accurately the propagation delays of such signals.
One conventional CAD simulation technique that is able to accurately determine the propagation delay of a signal through a circuit network calculates the delay based upon the actual physical characteristics (e.g., characteristic impedances, capacitances, etc.) of the branches of the network through which the signal propagates, as well as, the actual physical characteristics of the transmitter (e.g., output impedance, charging capacitance, etc.) and intended receiver (e.g., input impedance, charging capacitance, etc.) of the signal. These actual physical characteristics may be calculated by the CAD system based upon physical design data that describe physical features of the proposed design such as the physical layout of the design's circuit paths, the physical properties of the active and passive electronic components interconnected by those paths, etc., and well known physical laws that correlate these and other features of the proposed design to the physical characteristics to be calculated.
Unfortunately, in practice, it is often difficult or impossible to employ this conventional technique to simulate the operation of certain highly complex parallel processor designs (such as those described in the aforesaid copending applications). This is because, in practice, the amount of computer processing time (hereinafter termed “processing overhead”) required to accurately simulate the operation of such highly complex designs using such physical characteristics often is extremely large, and in extreme cases, can be prohibitive.
One proposed solution to this problem involves using so-called “hierarchical analysis” (HA) techniques. In HA, rather than basing the simulation of the design's timing operation upon the design's actual physical characteristics, the simulation is instead based upon approximate or estimated mathematical models of operation of portions of the design. That is, respective mathematical models are generated for respective functional blocks comprising the design which may be used to estimate the timing operation of the design. The design's timing operation is then simulated using these approximate models.
Unfortunately, although HA is able to reduce the amount of processing overhead needed to simulate a design's timing operation, it inherently introduces approximation error into such simulation. This causes timing operation simulations that are based solely upon HA-models to be inherently less accurate than timing operation simulations based upon actual physical characteristics.
This inherent inaccuracy of HA-based simulations results in certain disadvantages. For example, in order to try to ensure that the simulation uncovers all potential timing faults in the design, it may be necessary to adjust the simulation such that it is based upon worst case (i.e., most pessimistic) calculations of signal propagation delays in the design. Unfortunately, when “worst case analysis” is used, a sizable number of the timing faults identified by the simulation may actually be erroneous. This erroneous identification of timing faults may introduce significant inefficiencies into the design process. For example, a designer encountering an erroneous timing fault may believe that the fault actually is present in the design, and therefore, may unnecessarily modify the design to correct the supposed fault. This may unnecessary increase the time and expense required to formulate and validate the design.